TSMC eyes CoPoS packaging
TSMC is reportedly developing a new panel-level packaging technology designed to reduce manufacturing costs and support larger, more powerful AI processors.
TSMC is developing a new advanced packaging architecture known as Chip-on-Panel-on-Substrate (CoPoS), according to analyst Ming-Chi Kuo, as the semiconductor industry seeks more efficient ways to build next-generation AI processors.
The technology replaces traditional wafer-based packaging with panel-level processing, enabling improved material utilisation and support for larger package sizes.
The approach is expected to help accommodate increasingly complex AI accelerators that combine multiple compute chiplets with high-bandwidth memory (HBM).
Unlike some early reports, Kuo said glass is used only as a temporary carrier during manufacturing rather than forming part of the final package.
The completed package would continue to use conventional substrates while benefiting from improved production efficiency.
CoPoS is expected to complement, rather than replace, TSMC’s existing CoWoS packaging technology, which has become a critical enabler of AI hardware.
Reports suggest the new packaging platform could enter mass production around 2028.
As AI workloads continue to drive demand for greater computing performance and memory bandwidth, advanced packaging technologies are becoming increasingly important in enabling larger and more capable semiconductor systems.
