TSMC pushes CoPoS packaging
TSMC is developing its Chip-on-Panel-on-Substrate technology to support larger AI processors, with mass production reportedly targeted for the second half of 2028.
TSMC is advancing a new panel-level packaging technology designed to meet the growing size and performance requirements of next-generation AI chips.
Known as Chip-on-Panel-on-Substrate (CoPoS), the technology replaces conventional wafer-based packaging approaches with a panel-level process that uses rectangular substrates and glass-based materials.
The approach is expected to improve material utilization, support larger package sizes and enable higher integration densities for AI and high-performance computing applications.
According to industry reports, TSMC began installing equipment for a CoPoS pilot line earlier this year and is targeting mass production between 2028 and 2029.
The company previously unveiled a 310 mm × 310 mm CoPoS platform as part of its efforts to develop future advanced packaging solutions.
The technology is viewed as a potential successor to current wafer-based advanced packaging approaches for increasingly large AI processors.
By enabling larger package formats and reducing edge waste, CoPoS could help lower manufacturing costs while improving performance and scalability.
Industry analysts have suggested that future AI accelerators may be among the first products to adopt the technology as demand continues to grow for larger multi-die packages supporting advanced AI workloads.
The development highlights the increasing importance of advanced packaging innovation as semiconductor manufacturers seek new ways to improve performance, power efficiency and integration density beyond traditional process-node scaling.
