Synopsys and A*STAR advance packaging
Synopsys and A*STAR IME have launched a collaboration focused on simulation-led design for advanced packaging and chiplet architectures, targeting reliability and performance challenges in AI and HPC systems.
Synopsys and Singapore's Agency for Science, Technology and Research (A*STAR) have signed a Memorandum of Understanding (MoU) to advance semiconductor packaging and simulation technologies for next-generation chiplet and System-in-Package (SiP) architectures.
The collaboration will operate through the ASTAR IME–Ansys Joint Innovation Consortium for Semiconductor Excellence (JICSE), bringing together ASTAR's Institute of Microelectronics (A*STAR IME), Synopsys and participating industry and research organisations.
The initiative will focus on using digital modelling and simulation to identify packaging design, reliability and performance issues before physical prototypes are produced. This approach is intended to reduce development time and cost while improving manufacturability as package architectures become increasingly complex.
Initial research through JICSE will address mechanical design and analysis challenges including package and wafer warpage, thermo-mechanical stress, solder-joint reliability and moisture-induced failures. These issues become more significant as multi-chiplet packages increase in density and incorporate multiple materials and interconnect structures.
A*STAR IME will lead consortium-based R&D activities, drawing on its advanced packaging research platforms and industry-facing capabilities. The consortium will also work with academic institutions and provide technical training and seminars focused on simulation-led packaging design.
Synopsys will support the programme through access to its Ansys simulation software, providing trial licences to A*STAR IME and up to ten consortium member companies.
The collaboration reflects the growing role of simulation and modelling in advanced packaging development. As AI and high-performance computing systems increasingly rely on chiplets and heterogeneous integration, engineers need to evaluate mechanical, thermal and reliability behaviour across the package before committing to physical fabrication.
The partners aim to use the consortium to accelerate development and validation of advanced SiP technologies while building Singapore's capabilities in simulation-driven semiconductor packaging.
