CEA-Leti demonstrates hybrid ising machine
Researchers in France have combined memristors and stochastic magnetic tunnel junctions in a CMOS-compatible architecture, highlighting a potential route to vertically integrated hardware for energy-efficient optimisation.
Researchers from CEA-Leti, Spintec and C2N/Université Paris-Saclay have demonstrated a hybrid nanoelectronic Ising machine that combines hafnium-oxide memristors with stochastic magnetic tunnel junctions (SMTJs).
Published in Nature Communications, the work demonstrates an intrinsic annealing mechanism in which the two device technologies work together to search for solutions to combinatorial optimisation problems.
The architecture uses memristors to store the problem structure, while SMTJs provide stochastic binary variables that fluctuate naturally due to thermal noise. By controlling the read voltage of the memristor array, the researchers can progressively reduce this randomness as the optimisation process advances, allowing the system to move from exploration towards convergence.
The approach is designed to reduce data movement and digital instruction overhead by implementing parts of the optimisation algorithm directly through the physical behaviour of the nanodevices.
The prototype successfully solved graph-optimisation benchmarks, including a 24-vertex weighted MAX-CUT problem and a 10-vertex, three-colour graph-colouring problem. The experiments were conducted at room temperature and without an applied magnetic field.
From an integration perspective, the work demonstrates how different nanoelectronic technologies can be combined within a common hardware architecture. The memristors and magnetic tunnel junctions are compatible with CMOS processing and can be integrated in back-end-of-line (BEOL) layers.
The researchers suggest that this compatibility could support future 2.5D and 3D integration, bringing control electronics closer to the computing devices and reducing interconnect and data-transfer requirements. A more highly integrated implementation could also exploit parallel operation and the nanosecond-scale switching capabilities of the devices.
The current prototype relies on sequential updates and external feedback for measurement. Future work will focus on integrating control electronics closer to the devices, increasing problem sizes and exploiting parallel operation.
The team also plans to benchmark larger systems against conventional computing architectures in terms of speed and energy consumption. Such developments could help establish whether heterogeneous integration of memristive and spintronic devices can provide a scalable route to specialised optimisation accelerators.
