Teradyne and TEL target AI chip testing
Teradyne has partnered with Tokyo Electron (TEL) to introduce an integrated known good die (KGD) test solution designed to improve quality and yield in advanced 2.5D and 3D semiconductor packages for AI and data centre applications.
The production-ready solution combines Teradyne's UltraFLEXplus automated test platform with TEL's Prexa Singulated Device Prober (SDP), enabling high-precision testing of individual dies before they are assembled into chiplet-based packages.
As AI processors increasingly adopt heterogeneous integration and multi-die architectures, identifying defective dies before packaging has become essential.
A single faulty die can compromise an entire high-value package, making KGD screening a critical step in advanced packaging workflows.
The integrated test cell is designed for use by fabless semiconductor companies, foundries and outsourced semiconductor assembly and test (OSAT) providers.
TEL's Prexa SDP provides thermal management and supports the high-power characteristics of advanced AI devices, while Teradyne's UltraFLEXplus platform delivers production-grade electrical testing.
Built on an open ecosystem architecture, the solution is compatible with a range of probe cards, manipulators and interface technologies, allowing manufacturers to integrate it into existing production environments.
Shannon Poulin, president of Teradyne's Semiconductor Test Group, said the collaboration delivers a production-ready solution capable of meeting the thermal, power and performance demands of next-generation AI and data centre devices.
The companies showcased the jointly developed system at SWTest 2026, highlighting its role in supporting high-volume manufacturing of advanced 2.5D and 3D packaged devices.
