Chiplet summit 2026 highlights advanced packaging for AI
The fourth annual Chiplet Summit, taking place February 17–19, 2026, at the Santa Clara Convention Center, will focus on chiplet-based design, die-to-die interfaces, and AI acceleration, showcasing how advanced packaging is enabling higher performance, scalability, and cost efficiency.
The 2026 Chiplet Summit will bring together leading design and packaging engineers to explore the next wave of innovation in chiplet technology.
Sessions will cover die-to-die interfaces, high-bandwidth memory, and supercomputer-in-a-package solutions, providing insight into how chiplets allow faster design cycles, improved yields, and more powerful AI systems at lower cost.
“Chiplets allow system designers to implement the latest process nodes and packaging methods for AI applications, delivering flexibility, faster updates, and higher performance per watt,” said Chuck Sobey, Summit General Chair.
Keynote speakers and exhibitors include Synopsys, Cadence, Siemens EDA, Alphawave Semi, Marvell, the UCIe Consortium, Arm, and the Open Compute Project, giving attendees access to cutting-edge tools, technologies, and industry perspectives.
Lance Leventhal, Program Chair, added: “The Chiplet Summit has quickly become the go-to event for design and packaging engineers. This year’s event unites leaders across the ecosystem to address packaging challenges and drive the chiplet revolution forward.”
