AI fuels chip packaging boom
Rising AI demand drives investment in CoWoS and panel-level packaging as chipmakers race to expand capacity.
The rapid expansion of AI infrastructure is accelerating investment in advanced semiconductor packaging, with companies including Nvidia, AMD and TSMC seeking to increase production capacity for next-generation high-performance processors.
According to Reuters, advanced packaging has become a critical bottleneck in AI chip manufacturing, as increasingly complex processors rely on integrating multiple chiplets and high-bandwidth memory within a single package.
Research firm Yole Group forecasts that advanced packaging capital expenditure could approach $28 billion in 2026, with industry revenue expected to surpass traditional packaging for the first time.
TSMC continues to dominate chip-on-wafer-on-substrate (CoWoS) technology, widely used in AI processors from Nvidia, AMD and Broadcom.
However, capacity constraints are encouraging chipmakers to diversify their packaging supply chains.
Nvidia is reportedly providing billions of dollars in financing to support CoWoS capacity expansion at ASE Technology's subsidiary Siliconware Precision Industries (SPIL).
Meanwhile, Powertech Technology (PTI) is developing panel-level packaging as an alternative to conventional wafer-based approaches, working with AMD and Broadcom.
The company also plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore, with production potentially beginning in 2028.
TSMC is advancing its own chip-on-panel-on-substrate (CoPoS) technology, while equipment manufacturers including Applied Materials and Tokyo Electron are positioning themselves to benefit from growing demand for advanced packaging tools.
The investments highlight the semiconductor industry's increasing reliance on heterogeneous integration, chiplet architectures and advanced packaging technologies to deliver higher computing performance and support the expanding AI infrastructure market.
