CoWoS-L leads AI packaging race
TrendForce expects larger AI packages to drive adoption of TSMC’s CoWoS-L, while Intel’s EMIB-T gains traction as an alternative.
Growing AI chip demand is pushing advanced packaging towards larger package sizes and more complex integration of compute dies and HBM, according to TrendForce.
The research firm expects TSMC’s CoWoS-L to remain the mainstream advanced packaging solution for AI chips through 2028, despite increasing competition from Intel’s EMIB-T.
AI server chips have traditionally relied on CoWoS-S, which uses a silicon interposer to connect compute dies with HBM. However, as AI accelerators incorporate more compute dies and HBM modules, the size of the silicon interposer is approaching physical and manufacturing limits.
CoWoS-L addresses this challenge by incorporating high-speed silicon bridge dies within the interposer, allowing larger packages and greater flexibility in connecting compute dies and HBM. NVIDIA and AMD have already adopted the technology, while TrendForce expects AWS and Microsoft to follow in 2027.
Intel’s EMIB technology is also attracting interest as packaging requirements grow and TSMC’s advanced packaging capacity remains constrained. EMIB reduces reliance on large silicon interposers, although its routing density is limited by the package substrate.
Intel is addressing these limitations through improvements to line/space and microbump specifications, as well as EMIB-T, which incorporates through-silicon vias (TSVs) to shorten signal paths and improve module performance.
TrendForce expects Google to adopt EMIB-T in 2027, while AWS is also testing EMIB. However, the firm expects CoWoS-L’s technology maturity and yield advantages to keep it as the leading solution for AI chips through 2028.
