proteanTecs targets package-level monitoring
System-level analytics aim to improve visibility into chiplet interactions, package performance and reliability.
proteanTecs is highlighting the growing need for package-level monitoring as advanced packaging moves towards increasingly complex systems-in-package (SiP) architectures.
As compute dies, accelerators, HBM and other components are integrated using interposers, advanced substrates, TSVs and 3D stacking, interactions between chiplets and the package can create electrical, thermal and mechanical effects that are difficult to identify through conventional testing.
The company is extending its embedded monitoring and analytics capabilities across the SiP lifecycle, from wafer sort through packaging, production testing and in-field operation. The approach combines data from embedded monitors with manufacturing test equipment and other sources to provide visibility across multiple chiplets.
A key focus is pre-to-post packaging correlation, allowing engineers to compare parametric behaviour before and after integration. Changes in timing margin, voltage behaviour and other parameters can help identify effects associated with package power delivery, thermal gradients, warpage or mechanical stress.
proteanTecs also highlights the importance of monitoring package interconnects and power-delivery networks as the number of critical connections increases. For 3D architectures, the company points to the emerging concept of a Known-Good-Stack alongside traditional Known-Good-Die testing.
The company said package-aware analytics can help improve compound yield, reduce package scrap and support root-cause analysis by correlating timing, voltage and thermal behaviour across multiple dies.
As heterogeneous multi-die architectures become more complex, proteanTecs argues that semiconductor manufacturers increasingly need to assess not only whether individual dies operate correctly, but how they behave together within the finished package.
