From lab demonstration to pilot-line validation: Micro-transfer printing for heterogeneous integration

Micro-transfer printing (MTP) is moving from single-device demonstrations on individual chips to wafer-scale validation. At imec and Ghent University, the TRANSVERSE pilot line is evaluating whether this technique can meet the manufacturing metrics that matter for heterogeneous photonic integration: overlay, transfer yield, throughput, backend compatibility and post-transfer device performance and reliability.

BY Dr. Emadreza Soltanian, R&D Engineer, Dr. Emiel Dieussaert, Business Developer, Dr. Maximilien Billet, R&D Project Leader, Dr. Sarah Uvin, R&D Project Leader, Prof. Dr. Bart Kuyken, Co-Lead, Prof. Dr. Gunther Roelkens, Co-Lead, TRANSVERSE

Advanced photonic packages increasingly require functions that cannot be realized efficiently in a single process. Lasers, modulators, detectors and low-loss routing each favor different materials . No single platform can provide all of these functions with best-in-class performance. Silicon (SOI) enables dense routing and detector integration, but lacks efficient light sources and ultra-high-speed modulation. Silicon nitride (SiN) offers ultra-low-loss routing, but no active devices. Thin-film lithium niobate (TFLN) enables ultra-high-speed electro-optic modulation, while III–V materials are required for lasers, amplifiers and efficient photodetectors. Because these materials cannot be co-processed in a common front-end flow, they must be combined at the packaging level. Current approaches include flip-chip assembly on wafer level, wafer bonding and butt coupling of chips on module level. These are used in production today, but each comes with trade-offs in alignment complexity, integration density, throughput or process compatibility.

Figure 1: Schematic of coupon fabrication and micro-transfer printing process: a) Source wafer of thin film devices, b) Thin film devices coupon definition, c) Tether definition and coupons encapsulation, d) Releasing coupons by undercut etching the release layer, e) Coupon picking using a PDMS stamp, f) Coupon printing onto the target circuit, g) Parallel printing of coupons from multiple source wafers onto a target wafer.

Limits of existing integration approaches
A recurring limitation of existing approaches is that they often handle much more material than the final function requires. Large dies or full wafers may be bonded or assembled even when the required non-native devices occupy only a small fraction of the target chip area. This adds cost, increases process complexity and can couple the yield of otherwise independent platforms.

Figure 2: Wafer-scale printing of TFLN modulators onto a SiPh wafer. a) A 200mm SiPh wafer. b) microscope images of printed modulators on a 200mm wafer. c) cross-sectional schematic of the TFLN modulators on SiPh circuit. d) Alignment accuracy of printed coupons over the wafer. e) demonstrated performance of wafer-scale printing of TFLN modulators on a 200mm SiPh wafer.

Flip-chip assembly is mature and selective, but scaling to large device counts increases placement time and alignment overhead. Wafer bonding enables dense integration, but requires co-processing of dissimilar materials. Multi-chip integration on module level offers flexibility, but introduce optical loss and packaging complexity. As photonic systems become more complex, these limitations become more relevant. There is a need for an integration approach that combines:

• Selective placement of devices
• Highly efficient source and target material use
• Sub-micron placement accuracy
• Wafer-scale compatibility
• Compatibility with a wide variety of materials
• The integration on complex wafers without disrupting front-end processes

What micro-transfer printing adds
Micro-transfer printing offers a different integration strategy. Devices are fabricated and tested on their native source wafers, typically at high density. Only known-good, ultra-compact coupons are then transferred and printed onto the target wafer.

This allows III–V devices, TFLN modulators and silicon-based photonic circuits to be processed independently and combined afterwards, without forcing process compromises. The key question is no longer whether this concept works at device level, but whether it can meet manufacturing metrics such as:

• Overlay accuracy within wafer and from wafer-to-wafer
• Throughput per print cycle and per wafer
• Transfer yield
• Post-transfer device performance & reliability
• Compatibility with standard backend processing

This is the focus of the TRANSVERSE pilot line.

Micro-transfer printing in a nutshell
MTP is a parallel pick-and-place technique for integrating microscale devices from one wafer onto another. Devices are first fabricated on a source wafer and released using a sacrificial layer. A compliant stamp picks up these released device coupons and transfers them onto a target wafer. Multiple devices can be transferred in a single step, with sub-micron alignment.

Wafer scale validation: The TRANSVERSE pilot line
The TRANSVERSE pilot line addresses the step between laboratory demonstration and manufacturable process flow. The aim is not only to print individual devices, but to validate MTP on 200 mm wafers with controlled overlay, yield, repeatability and backend compatibility. Because each pick-and-place cycle takes roughly one minute, throughput depends on transferring many coupons in parallel. The pilot line is developing fully automated reticle-level printing as a route towards printing a full 200 mm wafer in under an hour, while respecting key manufacturing metrics such as:

• Overlay and placement accuracy across the wafer (< 500 nm 3 sigma)
• Transfer yield
• Throughput per print cycle and per 200mm wafer
• Repeatability across print cycles and wafers

In addition, the workflow includes backend steps such as passivation and metallization to connect with the silicon photonics platform, allowing evaluation of device performance after full processing, not just after placement. Initial results indicate that MTP can be operated as part of a wafer-scale process flow, rather than only as a sequence of isolated device demonstrations. Reliability evaluation is still ongoing, but no fundamental process-related showstoppers have been identified so far.

Figure 3: (a) Microscope image of an evanescently coupled InP UTC photodiode at C-band. (b) Frequency response of the device shown in (a) with a 2 × 12 µm² active region, showing bandwidth suitable for very high-speed photonic links.

Device-level proof points
Pilot-line validation only matters if the printed devices still perform as intended after transfer and backend processing. TRANSVERSE therefore evaluates both placement-level metrics and device-level results, including high-speed modulation and photodiode uniformity.

Demonstrated: High-speed TFLN modulators
TFLN modulators fabricated on their native wafers are transfer-printed onto silicon and silicon nitride circuits. TFLN is attractive because it combines low optical loss with very fast electro-optic modulation, but it is difficult to integrate directly into standard silicon photonics process flows.

Figure 4: Examples of transfer‑printed III–V amplifiers integrated on silicon photonic wafers, with representative optical characteristics.

Figure 5: Estimated MTP throughput as a function of the number of coupons transferred per print cycle, assuming a print cycle time of approximately one minute.

In this work, more than 600 pre-patterned coupons, incorporating TFLN waveguides, were printed with a transfer yield above 95% across multiple wafers. Here the yield is defined as the number of successfully printed coupons without any breakage. Measurements after integration show:

• Vπ·L of 2.8 V.cm
• Electro-optic bandwidth exceeding 70 GHz
• Low insertion loss of <2 dB

These values are consistent with the performance of the native devices. Results are obtained across multiple printed devices, indicating that alignment, transfer and backend processing do not introduce significant degradation.

Demonstrated: Photodiode uniformity
MTP of uni-traveling carrier (UTC) photodiodes (PDs) provides a second, complementary validation, implying that very small coupons less than 100 μm in size can be printed. The printed devices resulted in a waveguide-coupled photodiode with a responsivity of 0.3 A/W at 1550 nm with bandwidths going to 155 GHz at −1 V bias. The dark and saturation currents of this device are 10 nA and 4.5 mA, respectively.

Following this proof-of-concept demonstration, wafer-scale photodiode integration show uniform dark currents within and across wafers. These dark currents are also on par with the dark currents on the source wafer indicating minimal process-induced degradation. The current results are encouraging print yields of 99.9% and device yields of 97% across 500 photodiodes on a single target wafer show that the process holds up at scale. The photodiode results show that high yield is achievable; the next challenge is to combine this with higher throughput through fully automated reticle-level printing.

Ongoing: III–V lasers, semiconductor optical amplifiers and electro-absorption modulators
III–V lasers and semiconductor optical amplifiers have already been transfer-printed and shown to remain functional after integration. However, their full pilot-line evaluation, including yield statistics, array-level uniformity and reliability, is still ongoing. In parallel, the STARLIGHT project will evaluate micro-transfer printing of InP electro-absorption modulators.

What still needs to mature
While the current results demonstrate feasibility at pilot-line level, several aspects still need further development before production deployment. These include:

• Increasing throughput through reticle-level printing
• Co-design source and target for array printing and placement optimization
• Tighter integration with backend packaging processes
• Extended reliability testing and failure analysis under relevant operating conditions

In addition, broader validation across device types, particularly lasers and amplifiers, is still in progress.

Conclusion
Heterogeneous photonic integration is becoming a packaging challenge as systems combine low-loss routing, high-speed modulation, detection and light generation from different material platforms. Micro-transfer printing addresses this challenge by allowing devices to be fabricated on their optimal substrates, tested before integration and printed only where they are needed on a target wafer.

The TRANSVERSE pilot line shows how MTP can move beyond individual demonstrations toward controlled 200 mm wafer-scale validation. High-speed TFLN modulators and wafer-scale photodiode integration provide concrete proof points, including preserved device performance and encouraging yield data.

The next step is to combine these results with higher throughput, standardized layouts and extended reliability qualification, so that MTP can mature from a validated integration method into a production-ready process.