FAMES to present 3D integration advances
The European pilot line will showcase progress in 3D integration, hybrid bonding and heterogeneous integration technologies at ESSERC 2026.
The FAMES Pilot Line and the SiNANO Institute will present the latest advances in advanced semiconductor technologies, including 3D integration and heterogeneous integration, during a joint workshop at the European Solid-State Electronics Research Conference (ESSERC 2026) in Palma de Mallorca, Spain, on 7 September.
The half-day workshop, FD-SOI Pilot Line Insights and Perspective, will highlight technical progress achieved by the €830 million FAMES initiative, one of the five pilot lines established under the European Chips Act.
Presentations will span advanced FD-SOI technologies, embedded non-volatile memories, RF components, power management ICs and advanced integration technologies.
For the advanced packaging community, the programme will feature new developments in 3D sequential integration, including low-temperature process innovations enabling vertically integrated devices and the first millimetre-wave RF circuits fabricated using a full 3D sequential integration process.
The workshop will also highlight the growing role of heterogeneous integration in AI systems.
Researchers will present advances in small-pitch hybrid bonding and through-silicon via (TSV) technologies, which are being developed to support next-generation computing architectures that reduce data movement, latency and power consumption.
Additional presentations will cover Tyndall National Institute’s magnetics-on-silicon platform, including micro-transfer-printed inductors designed for integration into interposers and future buried power delivery networks.
According to the organisers, the workshop will provide attendees with an in-depth look at FAMES' latest technical achievements while offering opportunities to engage with researchers developing Europe's next generation of semiconductor technologies.
